Digital counting system



Dec. 5, 1961 EucHl GoTo 3,011,706

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' DIGITAL COUNTING SYSTEM Filed May 15, 1956 16 Sheets-Shes?l 9 Fig -J5- ll' 1 I l I I l Dec. 5, 1961 Enel-u GoTo DIGITAL couN'rING SYSTEM 16 Sheets-Sheet 10 Filed May l5, 1956 Dec. 5, 1961 EncHl GoTo DIGITAL COUNTING SYSTEM Filed May l5, 1956 16 Sheets-Sheet l1 Dec. 5, 1961 Eucl-u GoTo DIGITAL COUNTING SYSTEM Filed May l5, 1956 Fig@ J7- IZ/ I I E I l 16 Sheets-Sheet 12 A ia-cf?,

Dec. 5, 1961 Encl-u GoTo 3,011,706

DIGITAL COUNTING SYSTEM Filed May 15, 1956 16 Sheets-Sheet 13 Dec. 5, 1961 EucHl GoTo DIGITAL oouNTING SYSTEM Filed May 15, 1956 16 Sheets-Sheet 14 Dec. 5, 1961 EncHl GoTo DIGITAL COUNTING SYSTEM 16 Sheets-Sheet 15 Filed May 15, 1956 F i 19x16@ fla-@49767691 E,

Dec. 5, 1961 EncHl GoTo DIGITAL COUNTING SYSTEM Filed May 15, l1956 16 Sheets-Sheet 16 Fig-j9- United States vPatent G 3,011,706 DIGITAL COUNTING SYSTEM Eiichi Goto, 1416, 4-chome, Nakameguro, Meguro-kn, Tokyo-to, Japan Filed May 15, 1956, Ser. No. 585,043 Claims priority, application Japan May 21, 1955 6 Claims. (Cl. 23S-92) This invention relates to a digital counting system for electric signals and more particularly to a digital counter of electric signals.

Heretofore, in electric digital counters, vacuum tube circuits and transistor circuits have been widely used in combination with diode gating circuits.

However, the above-mentioned vacuum tube circuits and transistor circuits are expensive, unstable in their operation and low in their durabilities. On the other hand, digital counters which utilize magnetic cores, ferroresonance circuits, magnetic amplifiers or dielectric amplifiers, having hysteresis characteristics, have been recently proposed. However, these counters also have inherent limitations in that they are low in their durabilities and unstable in their operations, because they necessitate nonlinear resistances such as rectitiers.

A resonance circuit containing a nonlinear reactance element can be made to oscillate at the resonant frequency of said circuit by means of exciting said circuit with an A.C. signal having a frequency double that of said resonant frequency. The resonance circuit comprises a parametrically excited resonator which can assume one of two kinds of oscillation phases which are different by 180" from each other, for example 0 radian and 1r radian. Accordingly, when a weak alternating current signal having a resonant freqeuncy is applied to the resonant circuit of the parametrically excited resonator slightly prior to the application of the exciting alternating current, the oscillation phase of said resonator becomes either radian or a 1.- radian in accordance with the phase of the applied alternating current.

The system for transmitting binary phased alternating current signals or for carrying out an electrical computation by utilizing the principle as described above is more fully described in applicants copending U.S. patent application Serial No. 508,668, filed May 16, 1955, now Patent No. 2,948,818, and the parametrically excited resonators will be refeferred to as a parametron.

The purpose of this invention is to provide an electric digital counting system capable of counting the input electric signals by using parametrons.

Another object of this invention is to provide an electric digital counting system applicable easily for an electric digital counting system, in which binary information signals are represented by the phase of an A.C. current.

Still another object of this invention is to provide an electric digital counter capable of counting the number of input signals using a binary radix system.

A further object of this invention is to provide an electric digital counting system capable of counting the number of input signals according to any radix system such as quinary, decimal etc.

A still further object of thisV invention is to provide an electric digital counter capable of carrying out additive and subtractive countings of binary digits.

Other objects and many of theattendant advantages of this invention will be readily appreciated as the same `becomes better 4understood by reference to the following ice the following description) which is to be utilized in this invention as the circuit elements,

FIG. 1(a) shows the wave form of the voltage of the output terminals of the circuit of FIG. 1,

FIGS- 201), (b), (C), (d), (e) (f) and (g) are schematic symbol diagrams to be used for describing the operations 'of the embodiments of this invention,`

FIG. 3 shows wave forms of the exciting current to be supplied to the parametron circuit of the counter of this invention,

FIGS. 4(11) and (b) are schematic views of the binary digit register composed of parametrons,

FIGS. 5(a), (b), (c), (d), (e) and (f) are schematic views of the equivalent circuits of a parametron circuit,

FIG. 6 is a schematic view for the description of thc principle for constructing a reversi-ble counting circuit by using parametrons,

FIG. 7 is a schematic view for describing the operation of an embodiment of a reversible binary counter according to this invention,

FIG. 8 is a schematic view showing the operation of p a part of the reversible counter according to this invention,

FIG. 9 is a schematic view of another part of the reversible counter according to this invention,

FIG. l0 is a schematic View for describing the operation of an embodiment of a binary additive counter according to this invention,

FIG. 11 is a schematic view for describing the operation of an embodiment of a reversible counter of radix 4 according to this invention,

FIG. 12 is a schematic View for describing the operations o a counter of radix 3 according to this invention,

FIGS. l3(a), (b), (c) and (d) are different schematic views for describing the operations of four diierent embodiments of quinary counters according to this invention,

FIGS. 14(a) and (b) are schematic views for describing the operations of two different embodiments of counters of radix 6 according to this invention, v

FIGS. l5(a) and (b) are schematic views fordescribing the operations of two different embodiments of counters of radix 7 according to this invention,

FIGS. 16(a), (b), (c) and (d) are schematic views for describing the operations of four different embodiments of decimal counters according to this invention,

FIGS. 17(a), (b), (c) and (d )are schematic views for describing the operations of four different embodiments of counters of radix l1 according to this invention,

FIGS. l8(a), (b) and (c) `are schematic views for describing the operations of three different embodiments of the counters of radix 17 according to this invention, and

FIG. 19 is a schematic view for describing the operation of an embodiment of a counter of radix 57 according to this invention. Y

Referring to the parametrically excited resonator to be used in the present inventiomthe action of said resonator will be explained only simply herein, Ybecause it has been completely described in the specification of the abovementioned patent application Serial No. 508,668.

Parametric oscillation of any resonator or electric resonance circuit is elected by the fact that when the resonance frequency,V of which thvalu'eis about f, offga The generation of the above-mentioned 1/2 subharmonic oscillation is described as follows:

In FIG. 1, since the secondary windings wound on two ferromagnetic cores L1 and L2 which are inserted between the exciting terminals (1 and 1a) and the output terminals (2 and 2a) are wound to cancel their induced voltages, no voltage appears between the output terminals (2\ and 2a) even when an electric current is applied to the exciting terminals 1 and 1a. However, since the permeability of the ferromagnetic core is made to vary by said current, the resonance frequency of the resonant circuit connected to the terminals 2 and 2a varies.

Now, let it beassumed that the resonant circuit con- :nected to the output terminals 2 and 2a is in a resonant state with a frequency f and a weak resonant current I having a frequency f exists in the circuit. In this state, when an exciting current having frequency 2f is applied to the exciting terminals 1 and 1a, a voltage having the beat frequency of two frequencies 2f and f is induced in said resonant circuit due to cross modulation. As the beat frequency is equal to (2f-f) and equal to the frequency f of said weak resonant current if the phase of the beat voltage or the feed back voltage corresponds to the positive feed back direction capable of strengthening the weak resonant current, then the resonant current increases very rapidly, whereby an oscillation having frequency f (1/2 subharmonic of the exciting current having frequency 2f) is generated in the resonant circuit. The positive feed back is most effective in two phases which are different by 180 from each other. Accordingly, the oscillation having eitherone of the two phases is generated in the resonant circuit. The parametron represents l or of the binary digit according to the phase.

In general, parametric oscillation of the parametron having a frequency f vhas a remarkable character in that it can oscillate at only two dinerent phases which differ 'about V180 from each other, said oscillations being denoted, respectively, as an 0 radian oscillation and a 1r radian oscillation. It is 'possible to indicate one binary digitaccording to Vwhether the parametron is carrying out 'an 0 radian oscillation or a 1r radian oscillation. In

V ,signi51l-,beingcarriedout `just prior to application of the exciting Ycurrent towsaidrpararnetron. l

FIG. la illustrates the above. Two separate voltages at theou'tput terminals 2 and 2a of FIG. 1 are shown in Yi111 whichV the 'solid `line represents the oscilla- A Y, g l g th'e frequency fand phase of 0 and the rdotted `line Vrepresents the oscillation of frequency f having the phase of 180. When.an exciting Ycurrentgis applied to therve'xiitinfg terminals (1y and 1a) of FIG. 1 at the time A, the initial oscillation of small vamplitude increases very rapidly during the period between the times A and B "and then takes the steady state.Y Therp'hase of said steady jstate oscillation, as will be understood from FIG. la,

can be controlled by the phase of the weak initial oscillaition and this control canrbe achieved by restart of the parametron oscillation afterfinterruption of said oscillation...

The phase control ,signal Yof the parametron is applied tothe circuit from theV terminals Sand 3a of FIG. l, said -signal, causing the initialV oscillation so Y as to control Y the t oscillation of steady; state. When onee the oscillation he parametronvbecome's steaily, the Yphasefand amplithe Voscillation'of thesteady Vstate are not varied *even w'r the phase 'control signalY applied to the terminals 3 and 3a has ceased or the phase 'of said signal is finverted.. Accordingly, the next Ycontrol Vis carried out after interruption of the oscillation. The steady state oscillation of the parametron is taken out as an output from the terminals 2 and 2li and then used as the phase control signal of the parametron of the next stage.

The signal of the parametron is not a pulse and is a sinusoidal Wave having a phase modulation of 180. Accordingly, the parametron does not operate on a signal of one cycle and ordinarily operates on a signal of 3l0.cycles. In this manner, it is possible to amplify the signal current having a frequency f carrying a binary information in the form of phase different by 180, said signal current being hereinafter called the binary phased signal. The binary phased signal will also be called the phase controlling signal of the parametron.

In FIG. l is shown an embodiment of a parametron circuit to be used as the unit element in the binary counter of this invention.

VEach of the toroidal magnetic cores L1 and L2 having an output side diameter of 4 mm., inner diameter of 2 mm. and thickness of l mm. is made of a ferromagnetic material such as copper-zinc-ferrite. On said cores are wound primary windings having exciting terminals 1 and 1a and secondary windings, both said primary windings and both said secondary windings being, respectively, connected in series bucking and series aiding. Across the output terminals 2 and 2a of said secondary windings is connected a damping resistor Ra and a condenser C which forms a resonance circuit with said secondary windings. Let it be assumed that the resonance frequency of said resonance circuit is f. Then, if the inductance of the secondary windings of the parametron is made to vary by applying an alternatingcurrent having a frequency 2f to the input terminals 1 and 1aan oscillation having a frequency f Will be created in the resonance circuit. In this case, the alternating currents having a frequency 2f induced in the secondary windings cancel each other. In order to minimize the inductance variation Vin the secondary circuit, a D.C. bias signal may be superimposed on the primary windings. y

The phase of the oscillation current has a definite relation to the phase of the exciting alternating current supplied to the input terminalsl and' 1a. Moreover, it is possible to make the secondary circuit oscillate at two diierent phases which are different by 180 from each other Vand the oscillation current can be taken out from the output terminals 2 and 2a. Y

Accordingly, if a weak alternating current signal having a frequency f is applied to the oscillation circuit through a resistance R from the input terminals 3 and 3a at the same time as `or slightly prior to application of the exciting current to the exciting terminals 1f and 1a, the phase of the oscillation current is controlled by the phase of said weak current signals and assumes either one of two phases which are different byV 180 from each other, That is, if it is assumed4 that said two phases are 0 radian and 1r radian, respectively, an oscillation of 0 radian will becreated when the phase of the controlling current applied to the terminals 3 Yand 3a lis within the range between 0 and 7l' is Y radian and an Voscillation Vopfh1rrradian will be created when the phaseof said controlling current is Vwithin the range betweenr and `radian. Y y Y It is to be understood that althoughV the nonlinear unit element is illustrated asa ferromagnetic device, a nonlineart. capacitorucan also Vbe employed as theV nonlinear unit element'with identical koperational results.`

According tto this invention, an 4electric digitalcounter 1s constructed' by arranging said parametronsfin cascade 'above will be denoted hereinafter as an 0r Circuit.

groups, to all of said parametrons being applied an exciting alternating current having a frequency 2f.

Accordingly, each of the parametrons carry out a parametric oscillation having a frequency f having a phase of radian or 1rradian. Moreover, the oscillation output of each parametron is applied to a following parametron. Therefore, binary phased signals can be indicated in accordance with whether the alternating current having a constant frequency f has a phase of 0 radian or of 1r radian.

In the following description, it is assumed that binary digit 0 or l is indicated, respectively, in accordance with whether the phase of the alternating current signal is 0 radian or 1r radian and the input binary signal capable of converting the phase of alternating current to 0 radian or 1r radian will be, respectively, called in the followin description the signal 0 or signal 1. 1

A parametron as shown in FIG. l is schematically shown by a small circle in the systems of the following gures.

In FIG. 2(a), the terminals 4 and 5 correspond, respectively, to input terminals (3, 3a) for the phase controlling current and to output terminals (2, 2a) for the oscillation circuit as shown in FIG. l. The terminals for applying the exciting current signal are omitted.

In FIG. 2(b) is illustrated a parametron unit having three input terminals 4, 4a and 4b, to each of said terminals being applied a controlling current having a `frequency f, the amplitudes of the three applied controlling currents being almost equal. The parametron is a synchronous device and the timing for applying control currents will be explained later in FIG. 4.

The phase of each of the controlling currents becomes 0 radian or 1r radian in accordance with the signal 0 or 1. Accordingly, when the signal 0 is applied to two or three of said input terminals 4, 4a and 4b and the signal l is applied to any one of said terminals, the phase of the resultant controlling current becomes 0 radian, so that the parametron oscillates with a phase of 0 radian. In this case, the parametron sends out the signal 0. On the other hand, when the signal l is applied to two or three of said input terminals 4, 4a and 4b and the signal 0 is applied to any one of said terminals, the phase of the resultant controlling current becomes 1r radian. In this case, the parametron sends out the signal 1. In the normal operation of the parametron described, a signal of either phase is always applied to each terminal connected in the circuit.

As described above, when input terminals of an odd number are provided on the parametron and any input binary signal is applied to each of said terminals, the oscillation signal is determined in accordance with the majority of the input signals. As described above, when the oscillation of the parametron reaches a steady state, the phase and amplitude of the oscillation of the steady state are not varied even when the weak control signals of an odd number (the signals at the terminals 4, 4a and 4b of FIG. 2) are terminated or the phase of said signals is reversed.

Moreover, when any one of the input terminals 4, 4a and 4b in FIG. 2(b), say terminal 4 for example, is inthe condition of being always supplied with the signal 1, the oscillation signal becomes l in case of application of the signal l to any one of the remaining two terminals 4a and 4b and the oscillation signal becomes 0 only when the input binary signals of the terminals 4a and 4b are both 0. A parametron circuit as just described In the drawings, mark -lin the small circle representing a parametron denotes the existence of the above mentioned constantly applied signal 1, and the terminal -4 which is Vto be supplied constantly with the input signal l will be omitted. The schematic diagram of a parametron composing an Or Circuit is shown in FIG. 2(c).

On the other hand, when to the input terminal 4 in lation signal becomes l only when both the signals applied to the input terminals 4a and 4b are both l and said oscillation signal becomes 0 when either one or both of the signals of the terminals 4a and 4b are 0. A parametron circuit as just described above will be denoted hereinafter as an And Circuit. In the drawings, mark inscribed in the small circle denotes the existence of the above mentioned constantly applied signal 0, and the terminal 4 which is to be supplied constantly with the input signal 0 is omitted. The schematic diagram of an And Circuit is shown in FIG. 2(d).

As the control signal of a parametron is pure A.C., we can easily reverse the phase of the control signal before applying it to a parametron by inserting a phase reversing means such as a phase reversing transformer. In this case, the control signal l will be converted to 0 and similarly 0 to 1. Hence the insertion of a phase reversing means such as a phase reversing transformer has the functioning of a Not circuit (complementing circuit) and the insertion of such phase reversing means will be denoted by a short bar inscribed on the control signal line as shown in FIG. 2( e), i.e., FIG. 2|(e) is the abbreviation of FIG. 2(g), in which Tr is a phase reversing transformer.

ILet it be assumed that the symbol such as shown in FIG. 2U), in which any character x is marked in the small circle indicating a single parametron, means that a signal x besides the input signal supplied from the input terminals 4a and 4b is also supplied.

This symbol will be used, in order to simplify the drawings, to indicate the connection between the parametrons -as a substitute for coupling lines when the coupling lines in the drawing become too long or too complicated for writing it explicitly.

In the following, a general method for forming a logical circuit by using parametrons will be described.

A plurality of parametrons forming a parametron logical circuit are arranged in at least three groups. In the following description, only the case in which the number of said groups is just three will be treated, and the three groups will be, respectively, called groups I, Il and III.

The oscillations, of frequency, of the parametrons in each group are simulanteously interrupted and those of the three groups are successively interrupted. For providing said interruption, the exciting currents of frequency 2f which are interrupted as shown in FIG. 3 are applied to the parametrons of each group in such a manner that the currents I, II and III FIG. 3 are, respectively, applied to the groups I, II and III.

The exciting currents I, II and III which are slightly overlapping with one another are switched on and off one after another in a cyclic manner. Hence, the oscillations (of frequency f) of the parametrons of lthe group I become weak control signals of the parametrons of the group II and control the phase of the oscillations (of frequency f) of the parametrons of the group II. Similarly, the phase of the oscillations of the parametrons of the group III is controlled by the oscillations of the parametrons of the group II and the phase of the oscillations of the parametrons of the group I is controlled by the oscillations of the parametrons of the group HI.

In other words, the parametron logical circuit, a binary signal represented by a phase is transmitted successively .from a group of the parametrons to another group of the parametrons, namely, from group I to II, from II to III and from III to I. In the parametron logical circuit, three parametrons, one from each group and connected in a ring cascade as shown in FIG. 4(a), are used for the register of one binary digit. In FIG. 4(a), each of the groups is indicated by I, II or III at the top of the circle denoting the parametron.

As will be clear from the above description, the parametron is a synchronous device and such interruption of the excitation as shown in FIG. 3 achieves the function of a clock signal. Accordingly, if it is assumed that each V- 10s, aan Vand ses and dass notvary.

parametron shown in FIGS. 2(a), 2(b), 2(c), 2(d) or 2(1) belongs to either one of the three groups, say, to group I, the input signal of each parametron has to be switched on and off at the same time as the switching-on and on of the oscillation of the ygroup III or exciting current III of FIG. 3. Accordingly, the input signal to be applied to the counter of this invention, and to be denoted by the reference symbols A, S and/ or R in the following figures of the drawings, will also be synchronized. Accordingly, to apply `a binary digit l or once to an input terminal means the `fact that a signal having a frequency f and a phase of 180 or 0 is applied to the input terminal for one oscillation period of the parametron of one group (for example, in the above case of FIG. 2, group III).

In the following descriptions a parametron will be referred to simply as an element.

Referring to FIG. 4a, three elements 160, 200 and 300 are connected in ring-shaped or closed loop cascade connection and are, respectively, excited with exciting currents, I, II and III, so that, the oscillation phase of the element 200 is controlled by the oscillation output of the element 100, the oscillation phase of the element 300 is controlled by the oscillation output of the element 260, and the oscillation phase of the element i) is controlled by the oscillation output of the element 300. Accordingly, if the oscillation phase ofV the element 100 becomes Vthe value corresponding to binary digit l by application of the signal l to the input terminal 6, the signal l is held in the three elements in a circulating manner, even after the application of the input signal ceases. In all ofthe embodiments appearing later, it is to be understood that the circulating register composed of the abovementioned three parametrons is to be used always for lthe registration of one binary digit.

In the example in FIG. 4(a), the order of application of the exciting currents I, II and III is not limited to the hereinbefore described order and it may be possible to apply the exciting current I'to the element 200 and to apply, respectively, the exciting currents II and III to the elements 300 and 100.

In the following, the binary counter or scale of two circuit which is a basic circuit of this invention will be described.

FIG. 4(b) is a diagram of said scale of two circuit, in which the same symbols as described in FIG. 2 are used. VIn FIG. 4(b), an input signal to be counted is applied to the input terminal 7, said signal being an A.C. having a frequency f and the phase of which varies from zero to 180. Zero phase and 180 phase thereof represent, respectively, binary digit 0 or binary digit 1. Generally, said Vinput signal will be supplied from another element (parametron) belonging tothe group III. In FIG. 4(15), each of the elements (parametrons) 160, 260 and 30) forms a binary digit register as described in FIG. 4(a), Vand the element 409 represents a coupling element (coupling parametron). Now, if the input signal applied to the terminal 7 is a digit 0, the element 46u generates Y a signalfO owing to the signal 0 from the input terminal 7 andthe constant signal 0 represented by the symbo On the other hand, in the element 169,

Y the signal 0 from the terminal and the signal l represented by the symbol cancel each other rand only the signal from the element 300 becomes eiective. In the element 299, the signal l Sent from theelement 09 through the Not circuit (indicated bybar) Vand the constant signal 0 (indicated lby the symbo VV-) cancel each other and only the input from the element 1450 becomes effective. Y wherein the signalV 0 isapplied tothe input terminal 7,

Accordingly, during the period a binary digit 0 circulates through the three elements Nextpwhen a signal "l" is .applied to Vthe terminal 7 8 160, 200 and 300, the element becomes l and the element 400 'becomes 0, because signals 0 and l are, respectively, supplied from the element 300and the terminal 7, whereby the element 290 becomes l and further thereby the element 3G() becomes l; that is, the registered number varies from 0 to 1.

On the other hand, when a signal l is applied to the terminalV 7 during the state wherein the signal l has been registeredin the vbinary digit register composed of the elements lili), 200 and 300, both the elements 166 and 406 become 1, because signal l is suppiied from the element 305) and the terminal 7, whereby the element 200 becomes "0 and further thereby the element 300 becomes 0, That is, the registered number varies from l to 0. As a conclusion, the number registered in the binary digit register composed of the elements 10i), 200 and 300 does not vary in the case wherein signal 0 is applied to the terminal 7 and reverses in the case wherein signal l is applied to the terminal 7. Hence, the circuit operates as a scale of two circuit. This binary counting is performed in synchronism with the interruption of the exciting currents.

In this scale of two circuit, the coupling element (parametron) 49? becomes l only when both the signal from the terminal 7 and the registered number of the binary digit register are 1, i.e. in the case in which the scale of two circuit overflows. Hence, if the output of the coupling element 400 is used further as the input of another scale of two circuit of the next stage, a scale of 4 circuit will be obtained. Similarly, when n stages of said scale of two circuit are connected in cascade throughY respective coupling elements, a scale of 2n circuit will be obtained.

According to this invention, besides the above-mentioned scale of two circuit and scale of 2n circuit, a scale of 2n counter capable of counting the diilerence between two input signals and a scale circuit of other radix besides 2n can be obtained by modifying the above-mentioned scale of two circuit or scale of 2n circuit by the use of a few additional connections.

v In FIG. 4(1)), the excitation groups I, II and III may be changed. For example,'the elements 100 andr400, 20G, and 366 mayy belong, respectively, to the groups II, III, and I, or the elements and 400, 209, and 306 may be grouped, respectively, in the groups III, I, and II, because the interruption of oscillation varies cyclically in the order of I, ILIII, I, II

In the following, the elements 100, 200 and 300 will be called, respectively, as first, seco-nd and thi-rd elements of the binary digit Yregister of the scaleiof two circuit.

In FIG. 5(a), the input control signal x representing either a value of l or 0' is reversed at the phase reversing means (designated by a short bar) in the` input, hence theparametron designated by a circle will oscillate at signal 5 (the bar above means complementation) and the output thereof becomes clearly E. The circuit of FIG. 5(b) has obviously the equivalentY functioning to that of FIG. 5(a), because the input and output at both sides are the same. Y

VGenerally, by negating (reversing) all the inputsiof a parametron and also negating the output thereof-,one will obtain an equivalent circuit. For instance, in FIG. 5(,c), by negating the input :c and negating the input y (which has already one negation and` results in double negation, which is equivalent torno negation at all) and the input (which is a constant input l and changesto i.e.

a constant input "(l by negation), one obtains the equiva-V 

